The plants for the manufacture of integrated circuits have become very expensive. A modern wafer fabrication plant can cost in excess of $500 million. At the same time, there is a demand for inexpensive, complex integrated circuits. A critical factor in meeting this demand is the yield of good integrated circuits, i.e. the percentage of the integrated circuits that are fabricated that meet specifications published for the particular type of integrated circuit (IC). The current practice is for engineers to manually analyze failing circuits to ascertain the causes of the failing ICs.
These causes may be generally grouped under three headings: design errors; misprocessing which causes the parameters of basic circuit elements, such as resistors, capacitors, and transistors, to deviate from their design values; and random, localized process defects which cause individual ICs to fail. Examples of the localized process defects are (1) gate oxide defects which cause a transistor gate to short to the under lying substrate and (2) unopened contact vias which cause two nodes to fail to be connected. Design errors are usually identified early in the product life and once corrected are no longer of concern. Parametric failures are relatively easily monitored and detected by means of test patterns inserted onto the semiconductor wafer for this purpose.
Localized defects are much harder to identify. First the circuit fault that caused the failure must be located. Then the fabrication defect that caused the fault must be identified. Since localized defects arise from point contaminants or inhomogeneities in the processing environment and processing materials, they are always present to a certain extent. The goals of the yield improvement team are to identify which defects are most important in limiting yield and then to take appropriate action to reduce the occurrence of those defects.
The current practice is for an engineer to manually analyze failing units in order to identify the failure causes. This process is tedious and slow. For example, an engineer may only be able to analyze ten units per day. Unless one defect mechanism is overwhelming predominant, this is a statistically small sample. As a result, decisions made based on such a small sample may not attack the most important problems. Moreover, engineering analysis is usually only available on one shift, whereas the fabrication plants operate around the clock, seven days a week, in order to make maximum use of the huge capital investment. The consequence of this is that corrective action is delayed while waiting for the failures to be analyzed.
Computer technology has advanced to the point that the problem of analyzing failures arising from local faults to find the underlying defects has become practicable.